The subject matter disclosed herein relates generally to semiconductor devices. More specifically, the present disclosure relates to deep trench capacitor formation with a dual liner process.
In semiconductor devices, the capacitance value of a deep trench depends on the size of the deep trench area. The deeper the deep trench, the larger the capacitance value. In forming the deep trench, the deep trench implant can affect the electrical properties of the semiconductor device by laterally diffusing into the silicon-on-insulator (SOI) region.
In a first semiconductor technology (e.g., 32 nm technology), in order to protect the SOI region from the deep trench implant, a single spacer may be used. However, the thickness of this spacer prevents the opening of the deep trench in the substrate area from being as large as possible. This affects the capacitance value of the deep trench. In a second semiconductor technology (e.g., 22 nm technology), a highly-doped epitaxial layer may be formed between the buried oxide (BOX) layer and the substrate, so that no spacer is needed to protect the SOI region. However, it is difficult to control the out diffusion of the epitaxial layer and the wafer processing may be expensive. Further, the wafer substrate material is changed from a lightly-doped substrate to a substrate with a highly-doped epitaxial layer, which affects the type of devices this process can be used on.